Self-contained integrated circuit including adjacent cells of different types

ABSTRACT

An integrated circuit includes a stack having a semiconductor substrate with a first type of dopant, an UTBOX type buried insulating layer, electronic components, formed in the substrate, ground planes disposed beneath the buried insulating layer so as to be respectively plumb with corresponding components, wells with the first type of dopant, the wells being respectively beneath corresponding ground planes, and a bias circuit enabling distinct voltages to be applied to the ground planes by the wells. The wells are separated from the substrate by a deep well with a second type of dopant. The wells are separated from each other by a separating structure, which is either a lateral well having a second type of dopant or a block of insulating material.

CROSS REFERENCE TO RELATED APPLICATION

This application is the national phase under 35 USC 371 of internationalapplication no. PCT/EP2012/059519, filed May 22, 2012, which claims thebenefit of the priority date of French application no. 1154520, filedMay 24, 2011 and the priority date of France application no. 1158545,filed Sep. 26, 2011. The contents of the aforementioned applications areincorporated herein in their entirety.

FIELD OF DISCLOSURE

The invention pertains to integrated circuits and especially tointegrated circuits on a silicon-on-insulator (SOI) type substrate.

BACKGROUND

SOI technology consists in separating a fine layer of silicon (a fewnanometers thick) from a silicon substrate by a relatively thick layerof insulator (with a thickness of a few tens of nanometers as a generalrule).

Integrated circuits made with SOI technology have a certain number ofadvantages. Such circuits generally consume less electricity forequivalent performance. Such circuits also induce lower parasiticcapacitances, thus improving switching speed. Furthermore, the latch-upor parasitic triggering phenomenon encountered by MOS transistors inbulk technology can be avoided. Such circuits therefore are particularlywell suited to SoC or MEMS type applications. It is generally noted thatSOI integrated circuits are less sensitive to the effects of ionizingradiation and are hence more reliable in applications where suchradiation could cause operational problems, especially in spaceapplications. SOI integrated circuits can include, especially, SRAMrandom-access memories or logic gates.

Reducing the static consumption of logic gates while at the same timeincreasing their switchover speed is the subject of much research.Certain integrated circuits that are being developed integrate bothlow-consumption logic gates and high-switchover-speed logic gates. Togenerate both these types of logic gates on a same integrated circuit,the threshold voltage level of some transistors of high-access-speedlogic gates is reduced and the threshold voltage of other transistors oflow consumption logic gates is increased. In bulk technology, thethreshold level modulation of the same type of transistors is done bydifferentiating their channel doping level. However, in FDSOI (FullyDepleted Silicon-On-Insulator) technology, the doping of the channel isalmost zero (10¹⁵ cm⁻³). Thus, the channel doping levels in thetransistors cannot show big variations. This means that the thresholdvoltages cannot be differentiated by their channel doping levels. Onesolution proposed in certain studies for making transistors of the sametype with distinct threshold voltages is to integrate different gatematerials for these transistors. However, making such an integratedcircuit is impractical because it is technically difficult andeconomically prohibitive.

In order to have distinct threshold voltages for different transistorsusing FDSOI technology, there are also known ways of using a biasedground plane placed between a thin layer of insulating oxide and thesilicon substrate. By manipulating the doping of the ground planes andtheir biasing, it is possible to define a range of threshold voltagesfor the different transistors. One could thus havelow-voltage-threshold, or LVT transistors, high-voltage-threshold, orHVT transistors, and medium, or standard-voltage-threshold, also knownas SVT transistors.

For certain functions of the circuit, it is possible to combinetransistors of a same type, for example LVT or HVT transistors, in thesame region. However, certain functions of the circuit require thecontiguous joining of different types of transistors with ground planeshaving different biases. The design of such functions of the circuitproves to be relatively difficult because additional design constraintshave to be taken into account.

FIGS. 1 a to 1 c provide an example of pairs of transistors of differenttypes, respectively HVT, SVT, and LVT type transistors.

FIG. 1 a shows an example of a pair of HVT-type transistors, namely annMOS transistor 1 nH and a pMOS transistor 1 pH. The transistors 1 nHand 1 pH are made with SOI technology. The transistors 1 nH and 1 pH aremade on a silicon substrate layer 101H. The transistors 1 nH and 1 pHcomprise respective buried insulating layers, 103 nH and 103 pH,separated from the substrate layer 101H by means of respective groundplanes 102 nH and 102 pH and wells 112 nH and 112 pH. The insulatinglayers 103 nH and 103 pH are surmounted by an active silicon layer. Theactive silicon layer of the transistor 1 nH comprises a source, achannel 104 nH, and a drain. The active silicon layer of the transistor1 pH comprises a source, a channel 104 pH, and a drain. The groundplanes 102 nH and 102 pH enable the electrostatic control of thetransistor to be improved by limiting the penetration of the electricfields generated by the drain and the source beneath the channel 104 nHor 104 pH. The reduction of the lateral electrostatic coupling reducesshort-channel effects and limits the drain-induced depletion effect ordrain-induced barrier lowering (DIBL) effect. The channels 104 nH and104 pH are covered respectively with gate oxide layers 105 nH and 105pH. The gate oxides 105 nH and 105 pH are surmounted by respective gatestacks comprising metal layers 108 nH and 108 pH and polysilicon layers111 nh and 111 ph. The stacks are demarcated laterally by spacers 110 nHand 110 pH. Insulation trenches 106H, 107H and 109H are placed aroundthe transistors 1 nH and 1 pH.

To obtain HVT type transistors, the ground planes have a thickness knownas an ultra thin thickness, typically ranging from 10 to 100 nm. Theground plane 102 nH has P-type doping and is biased to ground, and theground plane 102 pH has an N-type doping and is biased to Vdd. The wells112 nH and 112 pH have respective P-type and N-type dopings. The groundplanes 102 nH and 102 pH are biased by means of wells 112 nH and 112 pHrespectively.

FIG. 1 b shows an example of a pair of SVT-type transistors, namely annMOS transistor 1 nS and a pMOS transistor 1 pS. The transistors 1 nSand 1 pS have substantially the same structure as the transistors 1 nHand 1 pH: they are made on a silicon substrate layer 101S comprisingrespective buried insulating layers 103 nS and 103 pS separated from thesubstrate layer 101H by means of the respective ground planes 102 nS and102 pS and wells 112 nS and 112 pS. The insulating layers 103 nS and 103pS are surmounted by an active silicon layer. The active silicon layerof the transistor 1 nS has a source, a channel 104 nS and a drain. Theactive silicon layer of the transistor 1 pS has a source, a channel 104pS and a drain. The channels 104 nS and 104 pS are covered respectivelywith gate oxide layers 105 nS and 105 pS. The gate oxide layers 105 nSand 105 pS are surmounted by respective gate stacks comprising metallayers 108 nS and 108 pS and polysilicon layers 111 nS and 111 pS. Thestacks are demarcated laterally by spacers 110 nS and 110 pS. Insulatingtrenches 106S, 107S and 109S are placed around the transistors 1 nS and1 pS.

To obtain SVT type transistors, the ground planes have an ultra-thinthickness. The ground plane 102 nS has an N-type doping and is biased toground and the ground plane 102 pS has P-type doping and is biased toVdd. The wells 112 nS and 112 pS have respective P-type and N-typedopings. The biasing of the ground planes 102 nS and 102 pS is done bymeans of the wells 112 nS and 112 pS respectively.

FIG. 1 c shows an example of a pair of LVT-type transistors, namely annMOS transistor 1 nL and a pMOS transistor 1 pL. The transistors 1 nLand 1 pL have substantially the same structure as the transistors 1 nHand 1 pH: they are made on a silicon substrate layer 101L comprisingrespective buried insulating layers 103 nL and 103 pL separated from thesubstrate layer 101H by means of respective ground planes 102 nL and 102pL and wells 112 nL and 112 pL. The insulating layers 103 nL and 103 pLare surmounted by an active silicon layer. The active silicon layer ofthe transistor 1 nL has a source, a channel 104 nL and a drain. Theactive silicon layer of the transistor 1 pL has a source, a channel 104pL and a drain. The channels 104 nL and 104 pL are covered respectivelywith gate oxide layers 105 nL and 105 pL. The gate oxides 105 nL and 105pL are surmounted by respective gate stacks comprising metal layers 108nL and 108 pL and polysilicon layers 111 nL and 111 pL. The stacks aredemarcated laterally by spacers 110 nL and 110 pL. Insulating trenches106L, 107L and 109L are placed around the transistors 1 nL and 1 pL.

To obtain LVT type transistors, the ground planes have an ultra-thinthickness. The ground plane 102 nL has N-type doping and is biased toVdd, and the ground plane 102 pL has P-type doping and is biased toground. The wells 112 nL and 112 pL have respective N-type and P-typedopings. The biasing of the ground planes 102 nL and 102 pL is done bymeans of the wells 112 nL and 112 pL respectively.

If pairs of HVT and SVT transistors can be attached together on the samerow or on adjacent rows, a pair of LVT transistors, on the contrary,cannot be adjacent to a pair of HVT or SVT transistors. Indeed, it canbe necessary to modify the biasing of the ground planes to ground or toVdd. Owing to these biases and dopings of the ground planes, shortingbetween wells or forward-biased P-N junctions can be generated.

SUMMARY

There is therefore a need for designs of integrated circuits of an FDSOItype in which the adjacent cells have wells of a same doping withdistinct biases to obtain distinct threshold voltages.

Besides, the invention generally seeks to favor the designing ofintegrated circuits having distinct threshold voltages.

Certain publications have proposed developments of structures of FDSOIintegrated circuits. One practical problem that arises with anytechnological development pertaining to such circuits is that theexisting design tools can prove to be incompatible or require majordevelopments in computer software.

Thus, in industry, the electronic circuit designers working forsemi-conductor manufacturers use computer-assisted design (CAD). The bigcircuits are indeed far too complex to be designed by hand and requireappropriate computer tools, especially to avoid risks of design errors.

CAD uses a functional specification at input. This functionalspecification describes the desired working of the circuit as well asthe non-functional constraints (such as surface area, cost, consumption,etc.). CAD then outputs a representation in the form of a computer file(generally in the GDSII format or more recently the OASIS format). Thiscomputer file defines the drawings of the masks of the integratedcircuit to be made, so that the masks can be fabricated. The masks madethen serve for the fabrication of the circuit in the semi-conductormanufacturing units, during the steps of photolithography. CAD isdivided into several steps.

Starting from the functional specification of the circuit, the conceptand overall architecture of the integrated circuit are defined in afirst step. Thus, the full system (hardware and software) is modeled ata very high level so as to validate the chosen architecture in terms ofperformance relative to the requirements of the application. Thearchitecture of the integrated circuit is generally designed in theVerilog, VHDL, SPICE or other languages.

Then, a floorplanning or optimizing step is carried out. In this step, aplan or map is created of the locations of the logic gates on the chip,the sources and the ground connections, and the inputs/outputs and themacro-circuits (i.e., the complex components such as the processors,DSPs, memories, etc.).

Then, a logic synthesis of the circuit is made. In this step, thecircuit is modeled at the register transfer level (or RTL). In RTLmodeling, the implementation of the integrated circuit is described inthe form of sequential elements and logic combinations between thedifferent inputs/outputs of the sequential elements and primaryinputs/outputs of the integrated circuit. The modeling gives a networkformed by logic gates and rudimentary elements. This modeling isgenerally encoded with a dedicated language such as Verilog or VHDL. RTLmodeling is automatically synthesizable in the form of combinatoriallogic gates (AND, OR, multiplexer and other gates) and sequential(synchronous D latches, etc.) logic coming from a standard cell library.The location of the elements is not yet specified at this stage andtakes the form of lists of elements needed to carry out the desiredfunctions.

Then, a behavioral synthesis of the circuit is made. This is also calleda high-level synthesis or algorithmic synthesis. Then, the temporalbehavior of the RTL model generated is simulated. Each interconnectionsignal is determined as a function of input stimuli described generallyin the same language as the RTL model. If the circuit to be simulatedcontains a processor, a corresponding executable program is defined inthe form of binary memory content. The memory containing the programcode and the data (FLASH, or SRAM for example) can also be modeled witha same language but at a level of abstraction higher than RTL.

The algorithmic synthesis is not necessarily sufficient to ensure theabsence of design errors for the following reasons: the generation ofthe stimuli is done by the designer and does not allow for performingexhaustive functional tests for reasons of time; and the logicsimulators are relatively slow. For a complex circuit, several days ofsimulation may be needed and this limits the number of simulations thatcan be made.

During a step of logic synthesis, the RTL model of the circuit isconverted into a description at the level of the logic gates i.e. thegate netlist is generated. A library of logic gates is available forthis purpose. This library is generally a collection of several hundredsof logic elements (such as AND gates, OR gates, flip-flop circuits,etc). This library depends on the fineness of etching of the circuit(for example 32 nm or 22 nm) and cell design rules depending on themanufacturer's method of fabrication.

The user must also furnish logic synthesis constraints such as frequencyof operation of the circuit, its conditions (range of supply voltage,temperature range, variations in gate crossing times related tofabrication methods), time constraints for starting and arriving at theprimary and secondary inputs of the circuit, the charging model linkedto the interconnection wires which will connect the gates or the maximumsize of the circuit on the silicon substrate.

The synthesis tools generally work on synchronous digital integratedcircuits, the sequential elements of which are clocked by a singleclock. As the case may be, there can be several clock domains combininga set of sequential and combinational elements. The logic synthesis toolof a synchronous circuit generally proceeds in several steps: the RTLmodel is converted into generic combinational and sequential logicelements (independently of the target library) following mathematicalalgorithms; the generic logic elements are replaced by those coming fromthe target library. To this end, the tool chooses the logic elementscomplying with the time and space constraints given by the user.Analytical computations of time limits are then performed on all thelogic paths of the circuit so as to make sure that they comply with thetime constraints (frequency of operation of the circuit). If the resultsare not conclusive, the tool tries to use other gates available in thelibrary to arrive at the desired result. It is thus common in a libraryto have numerous gates fulfilling the same logic function but withdifferent sizes and fan-out values; when the time constraints arefulfilled, the synthesis tool has certain time margins available oncertain paths. It can then optimize the designing of the circuit byreplacing certain gates by others that consume less intensively and needless silicon area while at the same time continuing to comply with timeconstraints.

The logic synthesis provides a computer file representing theinstantiation of the gates of the target library and theirinterconnection and representing the integrated circuit (this is thegate netlist). There are different formats of this type ofrepresentation, especially the Verilog format, the VHDL format or theEDIF format.

The logic synthesis is followed by a step of placing and routing. Duringthis step, the different components of the integrated circuit defined inthe gate netlist are automatically placed and connected according to theproblem to be resolved. Placing and routing is a difficult optimizationproblem that requires metaheuristic techniques.

Logic synthesis can require a lengthy and tedious re-definition of novelcomponents. Placing/routing can prove to be particularly sensitive tothe re-definition of novel components.

The invention seeks to resolve one or more of these drawbacks. Theinvention thus pertains to an integrated circuit comprising a stackconsisting of a semi-conductor substrate with a first type of doping, anUTBOX type buried insulating layer and a semi-conductor layer, andcomprising:

-   -   first and second electronic components formed in and/or on said        semi-conductor layer;    -   first and second ground planes beneath the buried insulating        layer so as to be respectively plumb with the first and second        electronic components;    -   first and second wells with the first type of doping disposed        respectively beneath the first and second ground planes.

The first and second wells are separated from the semi-conductorsubstrate by a deeply buried well or deep well with a second type ofdoping.

The first and second wells are separated from each other by a lateralwell having the second type of doping and/or by a block constituted byan insulating material.

The integrated circuit comprises a bias circuit enabling distinctvoltages to be applied to the first and second ground planes by means ofsaid first and second wells.

According to one variant, the first and second wells are separated fromeach other by a block constituted by an insulating material.

According to yet another variant, the block extends up to the deep well.

According to another variant, the block extends up to the first andsecond wells but not up to the deep well, and the block overhangs thelateral well presenting the second type of doping and separating thefirst and second wells.

According to yet another variant, the first and second wells areseparated from each other by a lateral well having the second type ofdoping.

According to one variant, a block of insulating material separates thefirst and second electronic components at the semi-conductive layerlevel, said block of insulating material being formed so as to be plumbwith said lateral well, the lateral well extending from the buriedinsulating layer up to the deep well.

According to another variant, said first electronic component is a firstFDSOI type transistor and the second electronic component is a secondFDSOI type transistor, one among the first or second transistors beingof an nMOS type, the other among the first or second transistors beingof a pMOS type.

According to yet another variant, the integrated circuit comprises:

-   -   a third transistor formed in and/or on said semi-conductor layer        and being of the same type as the second transistor;    -   a third ground plane disposed beneath the buried insulating        layer plumb with the third electronic component;    -   a third well with the first type of doping disposed beneath the        third ground plane in the continuity of the second well.

According to yet another variant, the third ground plane is of a typeopposite that of the second ground plane.

According to one variant, the third ground plane is of the same type asthe second ground plane.

According to another variant, a block of insulating material separatesthe second and third transistors at the semi-conductor layer level.

According to yet another variant, the block of insulating material doesnot reach the second and third wells.

According to yet another variant, the first ground plane has the secondtype of doping and is separated from the lateral band by an additionallateral band having the first type of doping.

According to one variant, the block of insulating material reaches thesecond and third wells but does not reach the deep well.

According to yet another variant, the first and second electroniccomponents are first and second transistors belonging to a SRAM memorycell.

According to another variant, the buried insulating layer has athickness smaller than 50 nm and the width of the gate of thetransistors is smaller than 50 nm.

DESCRIPTION OF THE DRAWINGS

Other features and advantages of the invention shall appear from thefollowing description given by way of an indication that is in no wayexhaustive, with reference to the appended drawings, of which:

FIGS. 1 a to 1 c are views in section of pairs of FDSOI transistors ofdifferent types according to the prior art;

FIG. 2 is a view in section of an integrated circuit according to afirst embodiment of the invention;

FIG. 3 is a view in section of an integrated circuit according to asecond embodiment of the invention;

FIGS. 4 a, 4 b, 5 a, 5 b, 6 a, 6 b, 7 a and 7 b are schematic views ofstandard cells according to the first embodiment for a library of aplacing/routing software for computer-assisted designing of theintegrated circuit;

FIG. 8 is an example of a portion of a circuit according to theinvention designed with the standard cells;

FIG. 9 is another example of a portion of a circuit according to theinvention designed with other types of standard cells;

FIG. 10 is another example of a portion of a circuit designed accordingto the invention with standard cells;

FIG. 11 is a graph illustrating the depletion width in a well as afunction of its depth and its bias voltage;

FIGS. 12 to 15 are different views in section of variants of integratedcircuits according to the invention;

FIG. 16 is a schematic illustration of a view in section of the top ofan integrated circuit 4 at the level of the wells;

FIG. 17 is a schematic view in section at the wells of a first exampleof an integration zone;

FIG. 18 is a schematic view in section at the wells of a second exampleof an integration zone;

FIG. 19 illustrates the drawing of a 6T type memory cell with biasvoltages according to the invention.

DETAILED DESCRIPTION

In general, the invention seeks to favor the designing of integratedcircuits having distinct threshold voltages.

The invention proposes on the one hand an integrated circuit having twoadjacent cells. The first cell comprises an nMOS transistor and a pMOStransistor of an FDSOI type. The second cell comprises an nMOStransistor and a pMOS transistor of an FDSOI type. These transistorshave ground planes and respective wells separating an ultra-thin buriedoxide layer (UTBOX) of the semi-conductor substrate.

The ground planes of the transistors of a same cell have respective Pand N dopings. The wells of the transistors of a same cell haverespective P and N dopings. A bias circuit is configured to applydistinct voltages to said P-doped wells.

The P doped well of one of the the transistors of the second cell isseparated from the first cell and the semi-conductor substrate by adeeply buried N-doped separation well.

With a simple structure and design rules requiring minimum adaptation ofthe existing tools of computer-assisted design, the invention enablestransistors of very different types to be attached together, thesetransistors having bias values and dopings that are distinct from theirground plane to obtain distinct voltage thresholds in order to meetdifferent design constraints.

FIG. 2 is a view in cross-section of two cells disposed in adjacent rowsr_(i) and r_(i+1) of an integrated circuit 2 in a first embodiment ofthe invention. The longitudinal direction will define the direction ofextension of the rows and the transversal or crosswise direction willdefine the direction in the plane of the substrate perpendicular to thelongitudinal direction. The integrated circuit comprises first andsecond FDSOI transistor cells.

The first cell 2H comprises an nMOS transistor 2 nH attached to a pMOStransistor 2 pH. The transistors of the first cell are of a first type,typically of an HVT type, i.e. with a high voltage threshold.

The second cell 2L comprises an nMOS transistor 2 nL attached to a pMOStransistor 2 pL. The transistors of the second cell are of a secondtype, typically of an LVT type, i.e. with a low voltage threshold.

The nMOS transistors of the different cells of the same row are aligned.The pMOS transistors of different cells of the same row are alsoaligned.

In a known manner, the transistors of the first and second cellscomprise a buried insulator layer 203 made so as to be plumb with aP-type silicon substrate 201 and surmounted by an active silicon layer.The active layer of the transistors has a known structure that is shownonly schematically for the sake of simplification. For example, thestructures of active layers described in detail with reference to FIGS.1 a, 1 b and 1 c could be used. The active silicon layer of eachtransistor has a source, a channel and a drain. The transistors are madewith FDSOI technology and the doping of the channel is therefore almostzero and substantially equal to the doping of the substrate 201. Thesubstrate 201 has for example a doping of 3*10¹⁵ cm⁻³. The channel of atransistor is lined with a gate oxide layer. The gate oxide issurmounted by a stack of gates comprising a metal layer (typicallyhaving a width smaller than 50 nm) and a polysilicon layer. The stack isdemarcated laterally by spacers. The transistors are separated byisolating trenches 206, 207 and 209.

The transistors 2 nH and 2 pL comprise ground planes 202 nH and 202 pLand wells 212 nH and 212 pL, with P-type doping disposed so as to beplumb with the buried insulator layer 203. The transistors 2 pH and 2 nLcomprise ground planes 202 pH and 202 nL, and wells 212 pH and 212 nL,with N-type doping disposed so as to be plumb with the layer of buriedinsulator 203. The ground planes 202 nH, 202 pH, 202 pL and 202 nL areprepared respectively on the wells 212 nH, 212 pH, 212 pL and 212 nL.The ground planes 202 nH, 202 pH, 202 pL and 202 nL extend in depth upto an intermediate level of the insulating trenches 206, 207 and 209.The wells 212 nH, 212 pH, 212 pL and 212 nL extend from the groundplanes 202 nH, 202 pH, 202 pL and 202 nL until they are beneath theinsulation trenches 206, 207 and 209. The ground planes and the wellscan have a doping of 10¹⁸ cm⁻³. The wells 212 pL and 212 pH areadjacent. The wells are biased by connections that are not shown. Eachground plane makes it possible to improve the electrostatic control ofits transistor by limiting the penetration of the electric fieldsgenerated by the drain and the source beneath the channel. The reductionof the lateral electrostatic coupling reduces short-channel effects andlimits the drain-induced depletion effect or drain-induced barrierlowering (DIBL) effect.

A bias circuit (not shown) is configured to enable the application of aground voltage to the ground planes 202 nH, 202 pL by means of the wells212 nH and 212 pL respectively. The bias circuit is also configured toenable the application of a voltage Vdd to the ground planes 202 pH, 202nL, by means of the wells 212 pH and 212 nL respectively.

In order to enable a modulation of the threshold voltage of thetransistors by playing on the biases and the doping of the groundplanes, the buried insulating layer 203 is of the UTBOX type, this typeof layer typically having a thickness of less than 50 nm. The insulatinglayer 203 can for example be made of silicon oxide.

With a layer of buried insulator of the UTBOX type, and with the biasesand the dopings of the ground planes mentioned, the transistors 2 nH and2 pH have raised threshold voltages and the transistors 2 nL and 2 pLhave lowered threshold voltages.

In the example illustrated in FIG. 2, the ground planes of the cells aresubjected to a FBB bias (or forward back biasing). The bias circuit ofthe ground planes is thus configured to modulate the voltages applied tothe ground planes relative to the ground voltage or the voltage Vdd. Inthe illustrated example, the biasing of the ground planes 202 nH and 202nL is thus increased by a voltage AV and the biasing of the groundplanes 202 pH and 202 pL is reduced by a voltage ΔV. The followingbiases are thus applied:

-   -   202 nH: 0+ΔV    -   202 pH: Vdd−ΔV    -   202 pL: 0−ΔV    -   202 nL: Vdd+ΔV

Thus, the P-doped wells of the two cells are biased with distinctvoltages. Depending on the value of AV, there is a risk of the wells 212nH and 212 pL being shorted through the substrate 201.

In order to prevent such shorting, one of the P-doped well transistorsis separated from the substrate 201 by means of a deeply buried well ordeep well with N-type doping. In the example illustrated in FIG. 2, thedeep well with N-type doping 222L is disposed so as to be plumb with thewell 212 pL. The deep well with N-type doping 222L also separates thewell 212 pL from the adjacent cell 2H so as to thus eliminate the risksof shorting or of a P-N junction forward biased with the cell 2H. Thedeep well with N-type doping 222L comprises a part 213L forming a bandthat projects crosswise to the adjacent cell relative to the well 212pL. At the longitudinal ends of the cell 2L, the band 213L extendscrosswise (for example in a transition cell) so that the well 212 pL issurrounded by the well 212 nL and the N-doped well 222L. One example ofa sizing of the width of this part 213L will be described in detail herebelow. The deep well 222L can, for example, be implanted up to a depthof more than 200 nm, typically of the order of 500 nm, beneath the layer203. The use of a deep well 222L enables the making of an insulation ofthe ground plane 202 pL relative to the adjacent cell up to a very greatdepth.

The well 212 pH is furthermore separated from the well 212 pL by meansof a band 213H with P-type doping (formed by a P-doped buried well)extending longitudinally. This band 213H projects crosswise relative tothe well 212 pH and is attached to the band 213L. At the longitudinalends of the cell 2H, the band 213H extends crosswise (for example in atransition cell) so that the well 212 pH is surrounded by a P-dopedwell.

The bias circuit can also be configured to apply the following biases tothe ground planes (FBB on the cell 2H and the cell 2L):

-   -   202 nH: 0+ΔV    -   202 pH: Vdd−ΔV    -   202 pL: 0+ΔV    -   202 nL: Vdd−ΔV

To avoid having to make forward-biased P-N junctions between the wells,the invention uses a maximum value ΔV of Vdd/2. Thus, with such abiasing, the difference in potential of a P-N junction is at the mostequal to −2*Vdd. The minimum width W_(min) of the bands 213L and 213Hpreventing a forward bias of a P-N junction will be defined by the gradeof the mask used for the implanting of the wells. This grade of mask isgenerally defined by a compromise between the fineness of etching andthe cost. For the 32 nm technological node, the minimum width permittedby the Design Rule Manual (DRM) is 270 nm. However, this value can besmaller with an implantation method optimized for FDSOI technology.

With a Vdd value of 0.9V, for a technological node sized 22 nm and aburied well doping of 10¹⁸ cm⁻³, numerical simulations show that thebands 213H and 213L having a width of two track pitches, namely 80 nm,prove to be sufficient. For rows initially having a width of 12 trackpitches, the rows made with cells according to the invention have anincrease in surface of the substrate limited to about 14%. A width ofthe bands 213H and 213L greater than 10% of the width of the row couldprove to be satisfactory in most cases to prevent the bands 213H and213L from being completely depleted.

Simulations show that the implantation of the buried well with a dopingof 10¹⁸ cm⁻³ can easily be made up to 700 nm for this size oftechnological node. FIG. 11 represents the depletion value W_(dep) as afunction of the depth DnWd of the buried well for different values ofthe voltage Vdd. This graph shows that a width of the bands 213H and213L of two track pitches proves to be sufficient to obtain animplantation of the buried well of up to 650 nm beneath the oxide layerfor these different bias values and to prevent the bands 213H and 213Lfrom being completely depleted.

Even if a width of the bands 213H and 213L is smaller than theserecommendations, this has no impact on the functioning: indeed, if thesebands are completely depleted, they behave like an extension in depth ofthe insulation trenches.

The ground planes, the wells and the deep wells could be made duringdifferent steps of the fabrication method. The implantation of the wellswill favor homogeneity of the charges. The implantation of the groundplanes will favor the doping at the interface with the layer of buriedinsulator.

FIG. 3 is a view in cross-section of two cells disposed in adjacent rowsr_(i) and r_(i+1) of a integrated circuit 3 according to a secondembodiment of the invention. The integrated circuit 3 comprises firstand second FDSOI transistor cells.

The first cell 3H comprises an nMOS transistor 3 nH attached to a pMOStransistor 3 pH. The transistors of the first cell are of a first type,typically of an HVT type, i.e. with a high voltage threshold.

The second cell 3L comprises an nMOS transistor 3 nL attached to a pMOStransistor 3 pL. The transistors of the second cell are of a secondtype, typically of an LVT type, i.e. with a low voltage threshold.

The transistors of the first and second cells comprise a layer of buriedinsulator 303 made so as to be plumb with a P-type silicon substrate 301and surmounted by an active silicon layer. The active layer of thetransistors has a known structure that is represented only schematicallyfor the purpose of simplification. The active silicon layer of eachtransistor comprises a source, a channel and a drain.

The transistors 3 nH and 3 pL comprise ground planes 302 nH and 302 pLand wells 312 nH and 312 pL, with P-type doping, positioned so as to beplumb with the layer of buried insulator 303. The transistors 3 pH and 3nL comprise ground planes 302 pH and 302 nL and wells 312 pH and 312 nL,with N-type doping disposed so as to be plumb with the layer of buriedinsulator 303. The ground planes 302 nH, 302 pH, 302 pL and 302 nL areprepared respectively on wells 312 nH, 312 pH, 312 pL and 312 nL. Theground planes 302 nH, 302 pH, 302 pL and 302 nL extend in depth up to anintermediate level of the insulation trenches 306, 307 and 309. Thewells 312 nH, 312 pH, 312 pL and 312 nL extend from the ground planes302 nH, 302 pH, 302 pL and 302 nL until they are beneath the insulationtrenches 306, 307 and 309. The ground planes are biased by connectionsthat are not shown.

A bias circuit, not shown, is configured to enable the application of aground voltage to the ground planes 302 nH and 302 pL by means of thewells 312 nH and 312 pL respectively, and to enable the application of avoltage Vdd to the ground planes 302 pH and 302 nL, by means of wells312 pH and 312 nL respectively. The layer of buried insulator 303 is ofthe UTBOX type.

With a layer of buried insulator of the UTBOX type, and with the biasesand dopings of the ground planes mentioned above, the transistors 3 nHand 3 pH have raised voltage thresholds and the transistors 3 nL and 3pL have lowered threshold voltages.

In the example illustrated in FIG. 3, the ground planes of the cells aresubjected to an RBB or reverse back biasing. Thus, the biasing of theground planes 302 nH and 302 nL is reduced by a voltage ΔV and thebiasing of the ground planes 302 pH and 302 pL is increased by a voltageΔV. The following biases are thus applied:

-   -   302 nH: 0−ΔV    -   302 pH: Vdd+ΔV    -   302 pL: 0+ΔV    -   302 nL: Vdd−ΔV

Thus, the P-doped ground planes of the two cells are biased withdistinct voltages. Depending on the value of AV, there is a risk of thewells 312 nH and 312 pL being shorted through the substrate 301.

In the example illustrated in FIG. 3, a well with N-type doping 322H isdisposed so as to be plumb with the well 312 nH. The deep well 322H alsoseparates the well 312 nH from the adjacent cell 3L so as to thuseliminate the risks of shorting or of a P-N junction being forwardbiased with this cell 3L. The deep well 322H has a part 313H forming aband projecting crosswise towards the cell 3L relative to the well 312nH. At the longitudinal ends of the cell 3H, the band 313H extendscrosswise.

The well 312 nL is furthermore separated from the well 312 nH by meansof a band 313L with P-type doping (formed by a doped buried well P)extending longitudinally. This band 313L projects crosswise relative tothe well 312 nL and is attached to the band 313H. At the longitudinalends of the cell 3L, the band 313L extends crosswise.

Depending on the configuration of the integrated circuit, the biascircuit can implement FBB or RBB type biases, either dynamically tomodify the threshold voltages as a function of the operating context ofthe circuit or statically following a step of initial configuration ofthe integrated circuit performed during its fabrication process.

FIGS. 4 a, 4 b, 5 a, 5 b, 6 a, 6 b, 7 a and 7 b are schematicrepresentations of standard cells designed to generate the topology ofan integrated circuit according to the invention by a placing/routingapplication of a system of computer-assisted design. These standardcells can be included in the library of the application to generate atopology of the integrated circuit with cells according to the firstembodiment. To make the drawings easier to read, the standard cells areillustrated in schematic section at the position of the wells.

The standard cell A (FIG. 4 a) corresponds to the cell 2H illustrated inFIG. 2. The standard cell FA (FIG. 4 b) corresponds to a transition cellthat is to be placed at a longitudinal end of a standard cell A toseparate it from an adjacent standard cell B of the same row. Thestandard cell A′ (FIG. 5 a) is a symmetrical version of the standardcell A. The standard cells A and A′ are disposed in adjacent rows sothat they can share power connectors. The standard cell FA′ (FIG. 5 b)corresponds to a transition cell that is to be placed at a longitudinalend of a standard cell A′ to separate it from an adjacent standard cellB′ of the same row. The transition cells comprise connections forbiasing the ground planes of the transistors of the standard cells.

The standard cell B (FIG. 6 a) corresponds to a cell of the 2L typedescribed here above. The standard cell FB (FIG. 6 b) corresponds to atransition cell that is to be placed at a longitudinal end of a standardcell B to separate it from an adjacent standard cell A of the same row.The standard cell B′ (FIG. 7 a) is a symmetrical version of the standardcell B and corresponds to the cell 2L illustrated in FIG. 2. Thestandard cells B and B′ are disposed in adjacent rows in order to beable to share power connectors. The standard cell FB′ (FIG. 7 b)corresponds to a transition cell to be placed at a longitudinal end of astandard cell B′ to separate it from an adjacent standard cell A′ of thesame row.

A library comprising such standard cells compliant with the inventioncan easily be implemented by a placing/routing application in order todefine the topology of the integrated circuit. The placing/routingapplication can thus use these standard cells in making their length(longitudinal direction of the row) vary during their insertion into thetopology of the integrated circuit, these standard cells having a samewidth. An existing placing/routing application can easily be modified totake account of the rules of positioning of these novel standard cells.

FIG. 8 gives an example of a topology of an integrated circuit preparedwith such standard cells. To generate this topology, the placing/routingapplication will typically use the width of these standard cells todefine the width of the rows in which these standard cells will bedisposed. Owing to the insulation obtained by the N-type deep wells ofthese cells, shorting currents between ground planes are prevented bothbetween adjacent rows and between adjacent cells of a same row. Thus, asillustrated in FIG. 8, the cells of the different rows are notnecessarily aligned in columns.

FIG. 9 gives another example of topology of an integrated circuit withother types of standard cells. The standard cells have the same width asthe prior-art standard cells. The standard cells A and B (as well as A′and B′) include transistors. These standard cells are insulated from oneanother only at their longitudinal ends by means of transition cells FABand FBA (or FAB′ and FBA′). A standard cell A or A′ is thus notseparated by a buried well from a standard cell B or B′ of an adjacentrow. To this end, the cells B and B′ are aligned in columns. Similarly,the cells A and A′ are aligned in columns. The standard cells of a samecolumn thus have a same length. This prevents shorting between P-dopedground planes by simply using the transition cells FAB, FBA, FAB′ andFBA′. Such a topology makes it possible to obtain an integrated circuitaccording to the invention with a silicon surface substantiallyequivalent to that of a prior-art integrated circuit.

FIG. 10 schematically illustrates the disposition of standard cells inan integrated circuit topology. Repetition cells Wt (known as well taps)are disposed at regular intervals in the rows by the placing/routingapplication in a known manner. The placing/routing application positionsthe standard cells A, A′, B and B′ between these well taps Wt andinterposes transition cells FAB, FAB′, FBA and FBA′ between standardcells A and B or between standard cells A′ and B′.

Different methods for generating a topology of integrated circuitsaccording to the invention can be envisaged in order to define thegeometry of the masks used during the fabrication process. The stepsprior to the placing/routing are known and shall not be described infurther detail.

According to a first variant, in a known manner, the placing/routingapplication can define a floor plan and then add the power rails. Theplacing/routing application can then position standard cells integratingbands 213L and 213H that project crosswise as illustrated in FIGS. 4 a,5 a, 6 a and 7 a. The placing/routing application can then positiontransition cells as illustrated in FIGS. 4 b, 5 b, 6 b and 7 b betweenthe standard cells. The placing/routing application can then dispose thewell taps at regular intervals. The clock tree can then be obtainedbefore defining the routing by a filling of interstices between standardcells with filler cells. This variant makes it possible advantageouslyfor the placing/routing application to generate the topology in usingthe usual rules for positioning standard cells.

According to a second variant, the placing/routing application candefine a floor plan and then add the power rails. The placing/routingapplication can then position standard cells having no bands 213L or213H (or 313L, 313H) that project crosswise, such as standard cellsillustrated in FIG. 9. The placing/routing application can then positioncorresponding transition cells between the standard cells. Theplacing/routing application can then dispose the well taps at regularintervals. The clock tree can then be made. The routing can then bedefined, followed by a filling of interstices between standard cells byfiller cells. The placing/routing application then interposes twocrosswise separation bands respectively with N and P doping betweencertain adjacent rows.

This variant advantageously enables the placing/routing application topreliminarily place standard cells according to the invention having thesame width as the prior-art standard cells before disposing separationbands crosswise only when this is necessary.

In most cases, the region of the integrated circuit including cells ofdifferent types (i.e. having P-doped wells that are distinctly biased)will have a proportion of cells of a first type that is much greaterthan the proportion of cells of a second type.

In this case, the placing/routing application could, for example,preliminarily place the cells of the second type (minority cells) andthen place all the cells of the first type (majority cells). The placingprocess could thus be accelerated, most of the cells of the first typebeing not adjacent to cells of the second type and thus having ewerplacement constraints.

Naturally, the placing/routing application could also preliminarilyplace the cells of the first type and then modify the placing of thesecells to introduce the minority cells of the second type.

In the designing of the integrated circuit, the minority cells could,for example, be selected when local time constraints appear during thelogic synthesis of the integrated circuit.

The examples illustrated in FIGS. 12 to 15 are intended to facilitatethe integration of different components while at the same time tobenefit from a great ability to modulate the threshold voltages of thedifferent components. In order to favor their integration, thecomponents in each of these embodiments have ground planes arranged inthe respective wells with a first type of doping. This type of doping isidentical to that of the semi-conductor substrate. These wells areseparated from the semi-conductor substrate by respective deep wellswith doping of a second type opposite the doping of the first type. Thewells with doping of the first type are separated by an insulatingmaterial. Thus, at least two of these components can dispose of groundplanes having distinct biases without requiring a major negative biasingof the semi-conductor substrate in order to avoid forward biased P-Njunctions.

In addition, these examples are particularly suited totopology-generating methods widely used for bulk technology.

In these examples, it is possible especially to use the same standardcell libraries as in the case of bulk technology. When generating themasks, it is enough to make minor changes to convert the bulk masks intomasks suited to FDSOI technology.

FIG. 12 illustrates an integrated circuit 4 including a zone 4Acomprising SRAM-type memory cells and a zone 4B comprising logic gates.The zone 4A comprises transistors each comprising a gate stack 451(corresponding to a pMOS transistor), 452 or 453 (corresponding to nMOStransistors). The zone 4B comprises especially transistors eachcomprising a gate stack 454, 455 (corresponding to nMOS transistors),456 or 457 (corresponding to pMOS transistors). The transistors of thezones 4A and 4B are made so as to be plumb with an ultra-thin buriedinsulating layer 441. The gate stacks 451 to 457 are made so as to beplumb with the respective ground planes 431 to 437. In this example, theground planes 431 to 434 and 436 comprise a P-type doping and the groundplanes 435 and 437 comprise an N-type doping. The ground planes 431 to437 are made on respective wells 421 to 427.

The wells 421 to 427 have a doping of a same type, in this case of aP-type. The wells 421 to 423 are made on a deep well 411 of an oppositetype to that of the wells 421 to 423 which, in this instance, are of anN-type. The wells 424 to 427 are made on a deep well 412 of a typeopposite that of the wells 424 to 427, thus of an N-type in thisinstance. The wells 411 and 412 are made in the semi-conductor substrate401 of a same type as the wells 421 to 427, i.e. of a P-type. The wells411 and 412 are separated from each other by the semi-conductorsubstrate 401. The deep wells 411 and 412 can thus be biased distinctly.The ground planes of the zone 4A can, for example, be biased at voltagesdifferent from those of the ground planes of the zone 4B.

An N-type junction extends between a contact pad and the deep well 411.This junction is made between two insulation trenches 461 and 462. Theground plane 431 and the well 421 are made between insulation trenches462 and 463 that extend from the insulation layer 441 up to the deepwell 411. The ground planes 432 and 433, as well as the wells 422 and423, are made between the insulation trench 463 and the insulationtrench 464 that extends from the insulation layer 441 up the deep well411. The biasing of the ground plane 431 and of the well 421 and of theground planes 432, 433 and of the wells 422, 423 can thus bedissociated.

An N-type junction extends between a contact pad and the deep well 412.This junction is made between two insulation trenches 467 and 468. Theground planes 436 and 437 and the wells 426 and 427 are made between theinsulation trench 467 and an insulation trench 466 that extends from theinsulation layer 441 up to the deep well 412. The ground planes 434 and435 and wells 424 and 425 are prepared between the insulation trench 466and an insulation trench 465 that extends from the insulation layer 441up to the deep well 412. The biasing of the ground planes 436, 437 andof the wells 426, 427 on the one hand and the ground planes 434, 435 andthe wells 424, 425 on the other hand can thus be dissociated.

The stacks 452 and 453 are separated by an insulation well 471 extendingup to the ground planes 432 and 433. The ground planes 432 and 433 canthus share the same bias. The stacks 454 and 455 are separated by aninsulation well 472 extending up to the ground planes 434 and 435. Theground planes 434 and 435 can thus share the same bias. The stacks 456and 457 are separated by an insulation well 473 extending up to theground planes 436 and 437. The ground planes 436 and 437 can thus sharethe same bias.

The deep well 411 is biased to voltage Vdds1 by means of an N-typejunction and a contact pad. The deep well 412 is biased to voltage Vdds2by means of an N-type junction and a contact pad. The ground plane 434(and therefore the ground plane 435) is biased to voltage Vb by means ofa contact pad. The biasing of the ground planes 431 to 433 and 436, 437is not illustrated but can be different from the biasing Vb.

With such an integrated circuit 4:

-   -   the set of transistors are made plumb with the wells of a same        type (P) thus facilitating the fabrication process;    -   owing to the use of deep insulation trenches, which extend up to        the deep wells, distinct biases can be applied on certain        adjacent ground planes, typically for different types of        transistors;    -   owing to the use of shallow insulation trenches, which extend        only up to the ground plane, identical biases can be applied to        certain adjacent ground planes by means of a common contact pad,        typically for transistors of the same type;    -   owing to the use of the deep wells 411 and 412, it is not        necessary to apply a highly negative voltage to the substrate        401 to prevent forward biased conductive junctions but rather,        it is enough to make sure that the voltage applied to the deep        wells 411 and 412 is higher than the maximum voltage that can be        applied to the different ground planes, a bias to ground        proving, for example, to be possible for the entire integrated        circuit 4, which make the design of the circuit even closer to        that of a bulk type design;    -   both types of distinct insulation trenches can be obtained by        means of only two etching masks; and    -   the insulation between the deep wells 411 and 412 enables the        application of different biases to them so as to better insulate        the memory cells from the logic gates.

With sufficiently high values of the bias voltages Vdds1 and Vdds2,there is a wide range available of variations of the bias voltages forthe ground planes 431 to 437.

FIG. 13 illustrates an integrated circuit 4 according to one variant ofthe integrated circuit of FIG. 12. This variant differs from theprevious one in the following characteristics:

-   -   the insulation trenches 461 to 468 extend in depth up to the two        wells 421 to 427 without reaching the deep wells 411 and 412;    -   the well 421 and the well 422 are separated laterally by an        N-type semi-conductor band;    -   the well 425 and the well 426 are separated laterally by an        N-type semi-conductor band; and    -   the well 423 and the well 424 are separated laterally from the        substrate 401 by means of respective N-type semi-conductor        bandsN-type.

The N-type semi-conductor bands ensuring a lateral separation aretypically residues of the step for implantation of the deep wells 411and 412. This makes it possible to avoid using specific etching masks.These lateral separation bands have a width sufficient to prevent theformation of untimely shorting.

For the example of FIGS. 12 and 13, the method for the automatedgeneration of the topology of the etching masks can begin with making alogic synthesis model of the integrated circuit 4 from a library ofstandard cells in bulk technology. The adjacent rows of transistors thencomprise an alternation of N-type wells and P-type wells. The logicsynthesis model is then converted to integrate an ultra-thin buriedinsulating layer and ground planes. Shallow insulation trenches are thenplaced longitudinally between the transistors of the same row. Deepinsulation trenches are then disposed between the rows with N-type wellsand the rows with P-type wells. The N-type wells are then systematicallyreplaced by P-type wells. These variations can thus be designed withdesign tools known in bulk technology, using particularly simpleconversion algorithms.

FIG. 14 illustrates an integrated circuit 4 according to a variant ofthe integrated circuit of FIG. 12. This variant differs from that ofFIG. 12 by the following characteristics:

-   -   the insulation trenches 461 to 468 extend in depth up to the        wells 421 to 427 without reaching the deep wells 411 and 412;    -   the insulation trenches 471 to 473 extend in depth up to the        wells 421 to 427 without reaching the deep wells 411 and 412;    -   the well 421 and the well 422 are separated laterally by an        N-type semi-conductor band;    -   the well 425 and the well 426 are separated laterally by an        N-type semi-conductor band; and    -   the well 423 and the well 424 are separated laterally from the        substrate 401 by means of respective N-type semi-conductor        bands.

The N-type semi-conductor bands ensuring lateral separation aretypically residues of the step of implantation of the deep wells 411 and412. This makes it possible to avoid using specific etching masks. Theselateral separation bands have a width sufficient to prevent theformation of untimely short circuits.

For the example of FIG. 14, the method of automated generation of thetopology of the etching masks can begin with making a logic synthesismodel of the integrated circuit 4 from a library of standard cells inbulk technology. The rows of adjacent transistors then comprise analternation of N-type wells and P-type wells. The logic synthesis modelis then converted to integrate an ultra-thin buried insulating layer andground planes. Deep insulation trenches are placed longitudinallybetween the transistors of a same row. Deep insulation trenches are thendisposed between the rows of N-type wells and the rows of P-type wells.The N-type wells are then routinely replaced by P-type wells.

FIG. 15 illustrates an integrated circuit 4 according to another variantof the integrated circuit of FIG. 12. This variant differs from that ofFIG. 12 by the following characteristics:

-   -   the insulation trenches 461 to 468 extend in depth up to the        ground planes 431 to 437 without reaching the wells 421 to 427;    -   the well 421 and the ground plane 431 are separated laterally        from the well 422 and the ground plane 432 by an N-type        semi-conductor band 481;    -   the well 425 and the ground plane 435 are separated laterally        from the well 426 and the ground plane 436 by an N-type        semi-conductor band 484;    -   the well 423 and the ground plane 433 are separated laterally        from the substrate 401 by means of an N-type semi-conductor band        482;    -   the well 424 and the ground plane 434 are separated laterally        from the substrate 401 by means of an N-type semi-conductor band        483;    -   the ground plane 435 is separated laterally from the band 484 by        means of a P-type lateral band 491 made out of the same layer as        the ground plane 434; and

the ground plane 437 is separated laterally from the junction 414 bymeans of a P-type lateral band 492 made in the same layer as the groundplane 436 The lateral separation bands 481, 484, 491 and 492 have awidth sufficient to prevent the formation of untimely short circuits.

For the example of FIG. 15, the method for the automated generation ofthe topology of etching masks can be the following: initially, a logicsynthesis model of the integrated circuit 4 is made from a library ofstandard cells in bulk technology. The adjacent rows of transistors thencomprise an alternation of N-type wells and P-type wells. The logicsynthesis model is then converted to integrate an ultra-thin buriedinsulating layer and ground planes. Shallow insulation trenches areplaced longitudinally between the transistors of a same row and shallowinsulation trenches are disposed between the rows of N-type wells andthe rows of P-type wells. N-doped lateral separators are positioned foreach row. A P-type lateral separator is positioned for each N-dopedground plane. The N-type wells are then routinely replaced by P-typewells.

In the examples of FIGS. 12 to 15, with a biasing of the deep wells at avoltage Vdds, the biasing voltages of the ground planes of thetransistors can be modulated as follows:

For an nMOS transistor:

-   -   in FBB type biasing, Vb is greater than 0, and the ground plane        is biased at Vb=0+ΔV, with ΔV≦Vdds; and    -   in RBB type biasing, Vb is smaller than 0, and the ground plane        is biased at Vb=0−ΔV, with ΔV≦|Vbd|−Vdds, Vbd being the reverse        breakdown voltage of the P-N junction.

For a pMOS transistor:

-   -   in FBB type biasing, Vb is smaller than Vdd, and the ground        plane is biased at Vb=Vdd−ΔAV, with ΔV≦|Vbd−Vdds+Vdd;    -   in RBB type biasing, Vb is greater than Vdd, and the ground        plane is biased at Vb=Vdd+ΔV, with ΔV≦Vdds−Vdd.

FIG. 16 schematically illustrates a top view in section of an integratedcircuit 4 at the level of the wells, this integrated circuit being madeaccording to the variant illustrated in FIG. 12. In this example, theintegrated circuit 4 has a first zone 4A of memory cells, a first zone4B of logic gates, a second zone 4C of memory cells and a second zone 4Dof logic gates.

The substrate 401 is biased to ground. The deep wells of the zone 4A to4D are biased respectively to Vdds1, Vdds2, Vdds3 and Vdds4.

FIG. 17 is a schematic view in section of the zone 4D at the level ofthe wells. One can distinguish a P-doped zone 42, forming wells of rowsr1 to r6 of transistors. It is possible to distinguish the N-dopedjunctions 414 intended for biasing a deep well with N-type doping. Azone 46 can be seen forming deep insulation trenches, insulating thejunctions 414 from the substrate 401 and insulating the rows of adjacenttransistors up to the deep well. Each row contains transistors of thesame type insulated by shallow insulation trenches. The adjacent rowsform an alternation of nMOS and pMOS transistors. The contact pads 415for contact with the ground planes, although present at a higher level,are illustrated in dashes in this figure for the sake of clarity.

FIG. 18 is a schematic view in section of the zone 4B at the level ofthe wells. A P-doped zone 42 forming the wells of rows r1 to r6 oftransistors can be seen. It is possible to distinguish N-doped junctions414 intended for biasing a deep well with N-type doping. It is possibleto distinguish a zone 46 forming deep insulation trenches, insulatingthe junctions 414 from the substrate 401 and insulating the rows ofadjacent transistors up to the deep well.

Each row contains transistors of the same type, insulated by shallowinsulation trenches. The adjacent rows form an alternation of nMOS andpMOS transistors.

In the adjacent rows r2 and r3, certain transistors are insulated fromthe rest of the transistors. These transistors comprise especiallyP-doped wells 428 and 429 separated from the rest of the P-doped zone 42by means of the deep insulation trench zone 46. These wells 428 and 429comprise a specific bias distinct from that of the zone 42. The wells428 and 429 are thus biased by means of contact pads 416. Thus,transistors with specific threshold voltages can be made plumb with thewells 428 and 429.

For the zone 4B of the example of FIG. 18, the method for the automatedgeneration of the topology of etching masks can be the following one.Initially, a logic synthesis model of the integrated circuit 4 is madefrom a library of standard cells in bulk technology. The adjacent rowsof transistors then comprise an alternation of N-type wells and P-typewells. The logic synthesis model is then converted to integrate anultra-thin buried insulating layer and ground planes.

Shallow insulation wells are placed longitudinally between thetransistors of the same row. Deep insulation trenches are then disposedbetween the rows of N-type wells and the rows of P-type wells. Deepinsulation trenches are then disposed around specific zones (defined bywells 428 and 429). The N-type wells are then routinely replaced byP-type wells.

The structures illustrated in FIGS. 12 to 15 are advantageouslyimplemented for SRAM memory cells. These structures indeed provide for adifferent biasing of the ground planes of the different transistors ofthe memory cell.

For the example of the 6T type SRAM memory cell as illustrated in FIG.19:

In read mode, it is sought to increase the threshold voltages of thenMOS transistors and lower the threshold voltage of the pMOStransistors. To this end, an RBB type of VBn biasing is done on theground planes of the nMOS transistors of the cell in passing from abiasing to ground to a biasing to −Vdd. An FBB type biasing VBp is doneon the ground planes of the pMOS transistors of the cell in passing froma biasing to Vdd to a biasing to ground.

In read mode, it is sought to increase the threshold voltages of thepMOS transistors and to lower the threshold voltage of the nMOStransistors. To this end, it is possible to carry out an FBB type VBnbiasing on the ground planes of the nMOS transistors of the cell, inpassing from a biasing to ground to a biasing to +Vdd. An RBB typebiasing VBp is done on the ground planes of the pMOS transistors of thecell in passing from a biasing to Vdd to a biasing to 2*Vdd.

Although the invention has been described with gate metal transistorshaving identical output work factors, the threshold voltages of thesetransistors can also be modified in forming gates with metals havingdistinct output work functions.

Although the different layers illustrated in the example (ground planes,wells, deep wells) are illustrated as being sharply dissociated, zoneshaving the same types of doping in distinct layers can of course comefrom the same step of the fabrication process, inasmuch as thefabrication process makes it possible to obtain layers havingdistinctive characteristics. The method must make it possible to obtainground planes having, on a given thickness, a concentration in dopingelements that is high enough to enable an effect to be had on thethreshold voltage of the transistors disposed so as to be plumb with thestructure. Usually, the concentration of the doping in the ground planesis greater than the concentration of the doping in the wells, forexample at least five times greater.

In the examples described, the adjacent cells are respectively nMOS andpMOS cells. It is also possible to envisage the application of theinvention to adjacent nMOS type cells or to pMOS type adjacent cells.

Having described the invention, and a preferred embodiment thereof, whatis claimed as new, and secured by Letters Patent is: 1-16. (canceled)17. A manufacture comprising an integrated circuit, said integratedcircuit comprising a stack having a semiconductor substrate with a firsttype of doping, an UTBOX type buried insulating layer, first and secondelectronic components, said first and second electronic components beingformed in a location selected from said group consisting of in saidsemiconductor substrate and on said semiconductor substrate, first andsecond ground planes disposed beneath said buried insulating layer so asto be respectively plumb with said first and second electroniccomponents, first and second wells with said first type of doping, saidwells being disposed respectively beneath said first and second groundplanes, and a bias circuit enabling distinct voltages to be applied tosaid first and second ground planes by means of said first and secondwells, wherein said first and second wells are separated from saidsemi-conductor substrate by a deep well with a second type of doping,and wherein said first and second wells are separated from each other bya separating structure selected from said group consisting of a lateralwell having a second type of doping and a block of insulating material.18. The manufacture of claim 17, wherein said first and second wells areseparated from each other by a block of insulating material.
 19. Themanufacture of claim 18, wherein said block of insulating materialextends up to said deep well.
 20. The manufacture of claim 18, whereinsaid block of insulating material extends up to said first and secondwells but not up to said deep well, and wherein said block overhangssaid lateral well presenting said second type of doping and separatingsaid first and second wells.
 21. The manufacture of claim 17, whereinsaid first and second wells are separated from each other by a lateralwell, wherein said lateral well has said second type of doping.
 22. Themanufacture of claim 21, wherein a block of insulating materialseparates said first and second electronic components at saidsemiconductor layer, said block of insulating material being formed soas to be plumb with said lateral well, said lateral well extending fromsaid buried insulating layer up to said deep well.
 23. The manufactureof claim 17, wherein said first electronic component comprises a firstFDSOI type transistor, wherein said second electronic componentcomprises a second FDSOI type transistor, wherein said first and secondFDSOI transistors comprise an nMOS type transistor and a pMOS typetransistor.
 24. The manufacture of claim 23, further comprising a thirdtransistor formed at a location selected from the group consisting of insaid first semiconductor layer and on said first semiconductor layer,wherein said third transistor is the same type as said secondtransistor, a third ground plane disposed beneath said buried insulatinglayer plumb with said third electronic component, and a third well withsaid first type of doping disposed beneath said third ground plane in acontinuity of said second well.
 25. The manufacture of claim 24, whereinsaid third ground plane is of a type opposite that of said second groundplane.
 26. The manufacture of claim 25, wherein a block of insulatingmaterial separates said second and third transistors at saidsemiconductor layer.
 27. The manufacture of claim 24, wherein said thirdground plane is of said same type as said second ground plane.
 28. Themanufacture of claim 27, wherein a block of insulating materialseparates said second and third transistors at said semiconductor layer.29. The manufacture of claim 26, wherein said block of insulatingmaterial does not reach said second and third wells.
 30. The manufactureof claims 29, wherein said first ground plane has said second type ofdoping and is separated from said lateral band by an additional lateralband having said first type of doping.
 31. The manufacture of claim 28,wherein said block of insulating material does not reach said second andthird wells.
 32. The manufacture of claims 31, wherein said first groundplane has said second type of doping and is separated from said lateralband by an additional lateral band having said first type of doping. 33.The manufacture of claim 21, wherein said first ground plane has saidsecond type of doping and is separated from said lateral band by anadditional lateral band having said first type of doping.
 34. Themanufacture of claim 26, wherein said block of insulating materialreaches said second and third wells but does not reach said deep well.35. The manufacture of claim 16, wherein said first and secondelectronic components are first and second transistors belonging to anSRAM memory cell.
 36. The manufacture of claim 16, wherein said buriedinsulating layer has a thickness smaller than 50 nm and said thicknessof a gate of said transistors is smaller than 50 nm.